This invention relates to digital logic circuitry and, more particularly, to arbiter circuits.
Two-input arbiter circuits are well known in the field of digital logic circuitry. An arbiter circuit responds to the respective application of asynchronous signals to its inputs to provide an output representation that is uniquely indicative of which of the input signals arrived first in time. If the input signals arrive at the same time, the circuit makes an arbitrary decision as to which input signal it will consider to have arrived first.
Conventional arbiter circuits commonly include a latch comprising cross-coupled gates. One of the problems frequently encountered in a circuit of this type is that the output of the latch may go through a metastable state which differs from the prescribed output digital states that the arbiter circuit is designed to provide. Also, the metastable states, if they occur, may be preceded by the generation of so-called rut pulses. If they appear at the output of the arbiter circuit, these pulses may provide false signals to associated circuitry.
U.S. Pat. No. 4,398,105 issued to P. J. Keller described an improved two-input arbiter circuit of the type that includes a latch comprising cross-coupled gates. A feature of the Keller circuit is that it blocks any metastable states of the latch (and any accompanying rut pulses) from appearing at the output of the arbiter circuit.
As designs in the field of digital logic circuitry have trended toward higher speed and lower power consumption, workers in the field have attempted to simplify the design of arbiter circuits such as those of the Keller type. It was recognized that these efforts, if successful, could provide an improved arbiter circuit more compatible with the requirements of modern-day high-speed low-power-consumption digital systems.